The invention relates to a digital arithmetic unit formed of a plurality of stages each having two half-adders combined into a full adder and a carry logic element which forms a carry from carries of half-adders to be supplied to a respective adjacent higher-order stage.
Arithmetic units of this type are known from the book by K. Reiss, H. Leidl and W. Spichall "Integrierte Digitalbausteine", Verlag Siemens Aktiengesellschaft, Berlin and Munich, 1970, pages 389-394, incorporated herein by reference. Their relatively low processing speed, however, is disadvantageous.
Shorter processing times are achieved with arithmetic units that function on the "carry-look-ahead" principle that is disclosed in the book "Microprocessors/Microcomputers" by D. D. Givone and R. P. Roeser, McGraw-Hill Book Company, New York 1980, pages 166-172, incorporated herein by reference. The N stages of an adder are preferably combined into respective K-place groups, whereby pre-calculated carries are supplied in parallel to the lowest order stages of all groups, said precalculated carries being formed in a carry generator from the input carry of the adder and the bits to be added. The carries between the individual stages of a group are then generally formed in the stages themselves. The carry generator, however, requires a considerable circuit expense which increases sharply with the desired processing speed and the processing width of the adder. An increase in the dissipated power and an increase in the circuit capacitances are also connected with these techniques.